1. Field of the Invention
The present invention relates to a test failure analysis technique for a semiconductor device, and more particularly, it relates to an OBIC (Optical Beam Induced Conductivity) observation technique.
2. Description of the Background Art
In order to improve the fabrication yield and the quality of a semiconductor device, it is requisite to carry out failure analysis of a product which is decided as defective in various tests during and after fabrication steps. A general technique of such failure analysis is as follows:
First, a point on a semiconductor chip causing a failure is found by electrical analysis. Then, a wiring metal, an interlayer isolation film or the like is removed by etching and a sectional hole is formed by a focused ion beam, to observe the point causing the failure with an electron microscope or the like. Thus, the cause of the failure is discovered. In relation to a recent semiconductor device which is complicated and highly densified, it is particularly important to find a portion causing a failure by the first step of electrical analysis. While such electrical analysis may be carried out by various techniques, the present invention relates to the so-called OBIC observation technique of detecting an OBIC current which is generated upon application of a light beam to a p-n junction in a semiconductor device and observing a defect and voltage distribution of the p-n junction.
FIG. 6 shows an exemplary OBIC observation method in relation to a sample of a CMOS inverter, whose chip is illustrated in section. The method shown in FIG. 6 is adapted to observe voltage distribution in a p-n junction.
The operation of the CMOS inverter shown in FIG. 5 is now described, in relation to generation of an OBIC current.
Referring to FIG. 6, a CMOS structure is defined by an n-channel MIS transistor which is formed by an n-type impurity diffusion layer 3a serving as a drain electrode, an n-type impurity diffusion layer 3b serving as a source electrode and a gate electrode 5a connected onto a portion of a p-type silicon substrate 1 between the drain and source electrodes through a gate dielectric film 9 and a p-channel transistor which is formed by a p-type impurity diffusion layer 4b serving as a drain electrode, a p-type impurity diffusion layer 4c serving as a source electrode and a gate electrode 5b connected onto a portion of an n-type well 1a between the drain and source electrodes through the gate dielectric film 9 on the n-type well 1a. The gate electrodes 5a and 5b are connected to an input terminal Vin in common, while the n-type and p-type impurity diffusion layers 3a and 4c are connected to an output terminal Vout in common. The p-type silicon substrate 1 is grounded through the p-type impurity diffusion layer 3c and a metal wire 13, while the n-type impurity diffusion layer 3b serving as a source electrode is also grounded through the metal wire 13. On the other hand, the n-type well 1a is connected to a power source 6 through the n-type impurity diffusion layer 4a and the metal wire 13, while the p-type impurity diffusion layer 4b serving as a drain electrode is also connected to the power source 6 through the metal wire 13.
When a negative voltage is applied to the input terminal Vin, the p-channel MIS transistor conducts so that a source voltage appears at the output terminal Vout. The n-channel MIS transistor is in an open state. In this state, therefore, a p-n junction between the n-type impurity diffusion layer 3a and the p-type silicon substrate 1 is reverse-biased to generate a high electric field.
When a light beam 10 is applied to this portion from a generally employed HeNe laser of 633 nm in wavelength, for example, pairs of electrons 11 and holes 12 are generated by a photovoltaic effect, as shown in FIG. 6. The holes 12 form an OBIC current, which in turn flows into the silicon substrate 1, and further flows into the ground through the p-type impurity diffusion layer 3c. This OBIC current is detected by an ammeter 7.
The OBIC current, which is thus generated by a photovoltaic effect, flows in a large amount since larger amounts of pairs of electrons 11 and holes 12 are formed in the p-n junction which is reverse-biased to generate a high electric field as compared with a non-biased p-n junction between the n-type impurity diffusion layer 3b and the silicon substrate 1, for example, irradiated with the light beam 10. Therefore, it is possible to recognize voltage distribution of the p-n junction by scanning the light beam 10 with respect to the surface of the semiconductor chip from the value of the OBIC current in the region irradiated with the light beam 10. This technique is briefly described in IEEE 21st Annual Proc. Rel. Phy., p. 118 (1983) by Daniel J. Burns et al., for example.
In the conventional OBIC observation technique, the light beam 10 cannot be applied to nor observed in a region of a p-n junction covered with the metal wire 13 of aluminum etc., such as the p-type impurity diffusion layer 4c shown in FIG. 6, for example, since the light beam 10 is applied from the side of a surface of the semiconductor chip which is provided with the device. In particular, a recent mass storage memory which is highly densified with a multilayered metal wire has substantially no region allowing detection of an OBIC current, and cannot be subjected to the test and analysis by this technique.